Global Leading University
Analog & RF Circuit and System Research Center


김소영 교수 | SOC 설계
학력 Education
  • (Ph.D.) in Electrical Engineering , Stanford University, Stanford, U.S.A. (2004)
약력/경력 Experience
  • Member of Consulting Staff, Digital Implementation, Cadence Design Systems, U.S.A.(2008-2009)
  • Senior CAD Engineer, Logic Technology Division, Intel Corporation, U.S.A. (2004-2008)
관심분야 Research Interest
  • VLSI interconnect and noise modeling and analysis
  • Signal Integrity and Power Integrity(SI and PI)
  • Electromagnetic Interference
연구키워드 Research Keyword
  • IC Design and Simulation
연구성과 Major Research Achievements
  • Models, Algorithms and Software Development for Parasitic Inductance Screening
  • EMI in Mobile Systems
  • SoYoung Kim and S. Simon Wong, "Closed-form RC and RLC Delay Models Considering Input Rise Time," IEEE Trans. on Circuits and Systems-I, Regular Papers, vol. 54, no. 9, pp. 2001-2010, Sept. 2007